Week 1, July 21

8:30-9:30 PM (IST)

Introduction to workshop

Week 2 July 28

8:30-9:30 PM (IST)

Introduction and Tool Installation

Week 3, August 4

8:30-9:00 PM (IST)

Basics of Hardware Description Languages (HDLs)

Week 3, August 4

9:00-9:30 PM (IST)

Combinational Logic Design

Week 4, August 11

8:30-9:30 PM (IST)

Sequential Logic Design

Week 5, August 18

8:30-9:30 PM (IST)

Introduction to Synthesis with Yosys

Week 6, August 25

8:30-9:30 PM (IST)

Static Timing Analysis with OpenSTA

Week 7, Sept 1

8:30-9:30 PM (IST)

Introduction to Simulation with Verilator

Week 8, Sept 8

8:30-9:30 PM (IST)

Physical Design - Floorplanning, Placement and routing

Week 9, Sept 15

8:30-9:30 PM (IST)

Introduction to Layout with Magic

Week 10, Sept 22

8:30-9:30 PM (IST)

Power Analysis and Optimization

Week 11, Sept 29

8:30-9:30 PM (IST)

Verification Techniques and DFT

Week 12, Oct 2

6:30-7:30 PM

Case Study 1